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Altera_Forum
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9 years ago

VHDL JK FlipFlop Error, Please help

Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals. So I've written a very simple code in ModelSim to make and simulate a JK FlipF...
Altera_Forum's avatar
Altera_Forum
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9 years ago

well as you can see I just mapped the signals in the testbench, there is a question here. should I also port map a signal in the JK code?