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Altera_Forum
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9 years ago

VHDL JK FlipFlop Error, Please help

Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals. So I've written a very simple code in ModelSim to make and simulate a JK FlipF...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Ive run and tested the code - I dont know what code you're compiling to get the error you are, but I just got an iteration error because Q depends on Qp which depends on Q. The errors you are reporting are because of the old issue. did you forget to recompile the code and restart the simulation?

To make this model correctly, you need to put delays between q and qp, but these are not synthessiable.