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Altera_Forum
Honored Contributor
Honored ContributorVHDL JK FlipFlop Error, Please help
Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals. So I've written a very simple code in ModelSim to make and simulate a JK FlipF...
Altera_ForumHonored Contributor
Honored ContributorAs I mentioned in a sentence before that sentence, I've corrected that mistake. Here is the full testbench code:
http://oi65.tinypic.com/15n95zc.jpg this code gives me those warnings. wierd. Here is the all VHDL files, I'd be glad if someone check them and see if they're working. download here (https://www.mediafire.com/?53t544z55q0hhea)
