VHDL Error. Type of identifier does not agree with it's usage

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std;

entity multi_main_file is

port(

Clock,reset: in std_logic

);

end multi_main_file;

architecture beh of multi_main_file is

component pc_adder_mul is

port(

add_in: in std_logic_vector(31 downto 0);

control: in std_logic;

add_out: out std_logic_vector(31 downto 0)

);

end component;

component and1 is

port(

and_in1: in std_logic;

and_in2: in std_logic;

and_out: out std_logic

);

end component;

component alu_control is

port (

instr_5_0: in STD_LOGIC_VECTOR (5 downto 0);

alu_op: in STD_LOGIC_VECTOR (1 downto 0);

alu_control_out: out STD_LOGIC_VECTOR (2 downto 0)

);

end component;

component control_unit is

port(

Instruction: in std_logic_vector(5 downto 0);

Reg_Dest: out std_logic;

Branch: out std_logic;

MemRead: out std_logic;

MemToReg: out std_logic;

ALUOp: out std_logic_vector(1 downto 0);

MemWrite: out std_logic;

ALUSrc: out std_logic;

RegWrite:out std_logic

--Jum: out std_logic;

);

end component;

component data_memory is

port(

MemWrite: in std_logic;

MemRead: in std_logic;

Clock: in std_logic;

address:in std_logic_vector(31 downto 0);

Write_Data: in std_logic_vector(31 downto 0);

Read_Data: out std_logic_vector(31 downto 0)

);

end component;

component instruction_memory is

port(

Instruction_Addr: in std_logic_vector(31 downto 0);

Instruction: out std_logic_vector(31 downto 0)

);

end component;

component alu is

port(

A: in std_logic_vector(31 downto 0);

B: in STD_LOGIC_VECTOR(31 downto 0);

alu_control: in STD_LOGIC_VECTOR(2 downto 0);

result: out STD_LOGIC_VECTOR(31 downto 0);

zero_flag: out STD_LOGIC

);

end component;

component program_counter is

port(

Clock: in std_logic;

PC_in: in std_logic_vector(31 downto 0);

PC_out: out std_logic_vector(31 downto 0)

);

end component;

component register_file is

generic(

Data_width:integer:=32;

Address_width:integer:=5

);

port(

Read_Reg_1: in std_logic_vector(Address_width-1 downto 0);

Read_Reg_2: in std_logic_vector(Address_width-1 downto 0);

Write_Reg: in std_logic_vector(Address_width-1 downto 0);

Write_Data: in std_logic_vector(Data_width-1 downto 0);

Read_Data_1: out std_logic_vector(Data_width-1 downto 0);

Read_Data_2: out std_logic_vector(Data_width-1 downto 0);

Mem_Write: in std_logic;

Clock: in std_logic

);

end component;

component shift_left_module is

port (

l_sh_in: in STD_LOGIC_VECTOR (31 downto 0);

l_sh_out: out STD_LOGIC_VECTOR (31 downto 0)

);

end component;

component sign_extender is

port(

exten_in: in STD_LOGIC_VECTOR (15 downto 0);

exten_out: out STD_LOGIC_VECTOR (31 downto 0)

);

end component;

component adder1 is

port(

Add_in1: in std_logic_vector(31 downto 0);

Add_in2: in std_logic_vector(31 downto 0);

Add_out: out std_logic_vector(31 downto 0)

);

end component;

component mux_32 is

port (

in1: in std_logic_vector(31 downto 0);

in2: in STD_LOGIC_VECTOR(31 downto 0);

mux_select: in STD_LOGIC;

mux_out: out STD_LOGIC_VECTOR(31 downto 0)

);

end component;

component mux_5 is

port (

mux_select: in STD_LOGIC;

in1: in std_logic_vector(4 downto 0);

in2: in STD_LOGIC_VECTOR(4 downto 0);

mux_out: out STD_LOGIC_VECTOR(4 downto 0)

);

end component;

component mux_alu is

port (

in1: in std_logic_vector(31 downto 0);

in2: in STD_LOGIC_VECTOR(31 downto 0);

in3: in std_logic_vector(31 downto 0);

mux_select: in STD_LOGIC_vector(1 downto 0);

mux_out: out STD_LOGIC_VECTOR(31 downto 0)

);

end component;

component or1 is

port(

in1: in std_logic;

in2: in std_logic;

out1: out std_logic

);

end component;

component mem_data_reg is

port(

clock: in std_logic;

in1: in std_logic_vector(31 downto 0);

out1: out std_logic_vector(31 downto 0);

end component;

component shift_left_26 is

port (

l_sh_in: in STD_LOGIC_VECTOR (25 downto 0);

l_sh_out: out STD_LOGIC_VECTOR (27 downto 0)

);

end component;

component instr_mem is

port (

datain: in STD_LOGIC_VECTOR (31 downto 0);

irwrite: in STD_LOGIC;

irout: out std_logic_vector(31 downto 0)

);

end component;

component tempreg is

port (

datain :in std_logic_vector(31 downto 0);

clk :in std_logic;

dataout out std_logic_vector(31 downto 0);

end component;

component mux_aluop is

port (

in1: in std_logic_vector(31 downto 0);

in2: in std_logic;

in3: in std_logic_vector(31 downto 0);

in4: in std_logic_vector(31 downto 0);

mux_select: in STD_LOGIC_vector(1 downto 0);

mux_out: out STD_LOGIC_VECTOR(31 downto 0)

);

end component;

signal s0,s1,s2,s3,s4,s5,s6,s8,s9,s10,s11,s12,s13,s14,s15,s17,s18: std_logic_vector(31 downto 0);

signal s16: std_LOGIC_VECTOR (31 downto 0);

signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c14,c15,c16: std_logic;

signal d1: std_logic_vector(4 downto 0);

signal c11,c12,c13: std_logic_vector(1 downto 0);

signal c17:std_logic_vector(3 downto 0);

signal w1: std_logic_vector(27 downto 0);

begin

s18(27 downto 0) <= w1(27 downto 0);

s18(31 downto 28) <= s1(31 downto 28);

mul1: pc_adder_mul port map(s0,c15,s1);

mul2: mux_32 port map(s1,s16,c3,s2);

mul3: data_memory port map(c5,c4,clock,s2,s13,s3);

mul4: instr_mem port map (s3,c7,s5);

mul5: mem_data_reg port map(clock,s3,s4);

mul6: register_file port map(s5(25 downto 21),s5(20 downto 16),d1,s8,s11,s10,c9,clock);

mul7: mux_5 port map(c8,s5(15 downto 0), s5(20 downto 16),d1);

mul8: mux_32 port map(s4,s16,c6,s8);

mul9: sign_extender port map(s5(15 downto 0),s9);

mul10: shift_left_module port map(s9,s17);

mul11: tempreg port map(s11,clock,s12);

mul12: tempreg port map(s10,clock,s13);

mul13: shift_left_26 port map(s5(25 downto 0),s18);

mul14: mux_32 port map(s12,s1,c10,s6);

mul15: mux_alu port map(s13,s9,s17,c11,s14);

mul16: alu_control port map(s5(5 downto 0),c17,c12);

mul17: alu port map(s6,s14,c17,s15,c16);

mul18: tempreg port map(s15,clock,s16);

mul19: mux_aluop port map(s15,s16,s18,c13,s0);

end beh;

mul19: mux_aluop port map(s15,s16,s18,c13,s0); error at s16.

it says type of identifier doesnot agree with it's usage.

thanks in advance. help appreciated !