Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

VHDL Error. Type of identifier does not agree with it's usage

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std; entity multi_main_file is port( Clock,rese...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Could you describe the problem you have? Just posting code (use code tags next time) and a question in the title makes it difficult to help you. Also, use descriptive names for signals. w17 does not help in debugging.