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Altera_Forum
Honored Contributor
Honored ContributorVHDL Error. Type of identifier does not agree with it's usage
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std; entity multi_main_file is port( Clock,rese...
Altera_ForumHonored Contributor
Honored ContributorI have basically done port mapping. The input and output provided in mux_aluop is the same as in the main file. Their types are same but still I can't figure it out where is the error .
