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Altera_Forum
Honored Contributor
8 years agoVHDL Error. Type of identifier does not agree with it's usage
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std; entity multi_main_file is port( Clock,rese...
Altera_Forum
Honored Contributor
8 years ago--mux32bit
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std; entity mux_aluop is port ( in1: in std_logic_vector(31 downto 0); in2: in std_LOGIC_VECTOR(31 downto 0); in3: in std_logic_vector(31 downto 0); mux_select: in STD_LOGIC_vector(1 downto 0); mux_out: out STD_LOGIC_VECTOR(31 downto 0) ); end mux_aluop; architecture behave of mux_aluop is begin process(mux_select) begin if mux_select = "00" then mux_out<=in1; elsif mux_select = "01" then mux_out<=in2; elsif mux_select = "10" then mux_out<=in3; end if; end process; end behave;