unsupported type when generating symbol

Question

I successfully compiled and used VHDL code in QII V9.1. Now I want to use the same code multiple times in a higher hierarchy block schematic. So I want to generate a symbol for this VHDL-code.

When trying to generate the symbol, I get an error 10071, meaning I use an unsupported type. And yes, I've defined my own type, but this compiles well in Quartus. Why this error when trying to generate a symbol? Any ideas?

altera_forum · Answer

Just use a VHDL entity/architecture in plain code as your top level, instead of using a graphical tool. You can use a tool such as Sigasi HDT to easily instantiate your components. This always works.

altera_forum · Answer

Because the graphic editor in quartus is very limited. It only likes std_logic_vectors.  Create a new top level VHDL. If its a repeated structure use a generate loop.

altera_forum · Answer

Yes I noticed. It still is strange, because on my VHDL top level I only use type std_logic. My own type is only used inside my VHDL code, which compiles well in Quartus, stand alone.

Well I've converted my type to std_logic and now it compiles.

But instead of

color <= green;

IF color = green THEN

I now use

color < "001";

IF color = ""001" THEN -- green

Although I use RTL VHDL, I prefer to use schematic instead of structural VHDL. Thanks for your replies.

altera_forum · Answer

The problem with schematics is that you wont be able to simulate them from Quartus 10+.   But why dont you just use constants to reference the colours to make it as readable as you had before?  
constant GREEN : std_logic_vector := "001";
if color = GREEN then
  .....

altera_forum · Answer

Hi Tricky,

Of course you're right.

This is as readable as my original code.

Well, it was the first time I used my own types.

Not very succesfull. Next time I'll stick to std_logic.

Thanks for the information about Quartus 10+

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unsupported type when generating symbol

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