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Altera_Forum's avatar
Altera_Forum
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16 years ago

unsupported type when generating symbol

I successfully compiled and used VHDL code in QII V9.1. Now I want to use the same code multiple times in a higher hierarchy block schematic. So I want to generate a symbol for this VHDL-code. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Because the graphic editor in quartus is very limited. It only likes std_logic_vectors.

Create a new top level VHDL. If its a repeated structure use a generate loop.