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Altera_Forum's avatar
Altera_Forum
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15 years ago

unsupported type when generating symbol

I successfully compiled and used VHDL code in QII V9.1. Now I want to use the same code multiple times in a higher hierarchy block schematic. So I want to generate a symbol for this VHDL-code. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

you could, but you lose all the support for proper typing that VHDL was designed for. you're stuck with std_logic(_vector)!