unsupported type when generating symbol

Yes I noticed. It still is strange, because on my VHDL top level I only use type std_logic. My own type is only used inside my VHDL code, which compiles well in Quartus, stand alone.

Well I've converted my type to std_logic and now it compiles.

But instead of

color <= green;

IF color = green THEN

I now use

color < "001";

IF color = ""001" THEN -- green

Although I use RTL VHDL, I prefer to use schematic instead of structural VHDL. Thanks for your replies.