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Altera_Forum's avatar
Altera_Forum
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17 years ago

Unable to place RAM cells in design

Hi folks,

I'm trying to work on an SoPC design. I've used my architecture as an IP and inserted it onto the SoPC having Nios II CPU, jtag-uart, interval timer, on chip memory, and a pio.

I'm trying to fit this device onto a Cyclone II EP2C20F484C7.

My IP's architecture uses DPRAM cells, around 32 of them with a depth of 150 bits each accessed 1 bit at a time. So the total usage during its compilation was ~ 4096 memory bits.

Now, after generating an SoPC, when i try to compile it, i get the following error:

Error: Cannot place 265 RAM cells or portions of RAM cells in design.

Please advice me as to what I should be doing.

btw, I'm an amateur as far as the quartus tool and SoPC are concerned.

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    seems to me that each of the 32 dprams should only use 1 M4K.

    http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1_03.pdf shows that the M4K can be configured to 4K x 1. It also show that the EP2C20 has 52 M4Ks. This would make me assume that the rest of the system is using the other 233 M4Ks(error message says cannot fit 265 RAM CELLS... 265 - 32(from the IP) = 233). What is the size of the on chip memory? Are there multiple instances of your custom IP?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I've set the size of the on-chip memory as 20kb.

    No, there's only one instance of my IP in the SoPC.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The design of the architecture is such that I'm using 32 components which in turn instantiates the identical DPRAM cells having 150 bits capacity each read/written 1 bit at a time.

    Total memory bits used by the IP is 4800 out of the available 239616 bits.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Take a look at the Compilation Report and look under Analysis & Synthesis -> RAM Summary. See if there is anything that jumps out at you. Maybe copy and paste it here. It doesn't show the M4K usage like the Fitter -> RAM Summary does but it may give clues.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The 32 DPRAMs at 150 x 1 will use up 147456 ram bits because they are blocked off in 4k blocks plus parity. Each M4K is 4608 bits(4096 + 512 parity bits). Each of your DPRAMs will use one M4K, thus, 32 * 4608 = 147456 bits. Thats 61.5% of the available ram bits.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    This is the summary of my IP's compilation report:

    --- Quote Start ---

    Total logic elements 1,859 / 18,752 ( 10 % )

    -- Combinational with no register 777

    -- Register only 224

    -- Combinational with a register 858

    Logic element usage by number of LUT inputs

    -- 4 input functions 492

    -- 3 input functions 635

    -- <=2 input functions 508

    -- Register only 224

    Logic elements by mode

    -- normal mode 1138

    -- arithmetic mode 497

    Total registers* 1,082 / 19,649 ( 6 % )

    -- Dedicated logic registers 1,082 / 18,752 ( 6 % )

    -- I/O registers 0 / 897 ( 0 % )

    Total LABs: partially or completely used 133 / 1,172 ( 11 % )

    User inserted logic elements 0

    Virtual pins 0

    I/O pins 45 / 315 ( 14 % )

    -- Clock pins 1 / 8 ( 13 % )

    Global signals 2

    M4Ks 2 / 52 ( 4 % )

    Total memory bits 4,800 / 239,616 ( 2 % )

    Total RAM block bits 9,216 / 239,616 ( 4 % )

    Embedded Multiplier 9-bit elements 0 / 52 ( 0 % )

    PLLs 0 / 4 ( 0 % )

    Global clocks 2 / 16 ( 13 % )

    Average interconnect usage 2%

    Peak interconnect usage 4%

    Maximum fan-out node clk~clkctrl

    Maximum fan-out 1039

    Highest non-global fan-out signal quad16:q16|nlfsr10:nlfsr_10|wradd[4]~731

    Highest non-global fan-out 520

    Total fan-out 8026

    Average fan-out 2.72

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Also, could you tell me how much of on-chip memory i should be allocating so that the SoPC would fit. I have no memory requirements?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    This is the resource summary of my SoPC:

    --- Quote Start ---

    Total logic elements Not available

    Total LABs Not available

    User inserted logic elements 0

    Virtual pins 0

    I/O pins 22 / 315 ( 7 % )

    -- Clock pins 0 / 8 ( 0 % )

    Global signals 14

    M4Ks 86 / 52 ( 165 % )

    Total memory bits 150,464 / 239,616 ( 63 % )

    Total RAM block bits 396,288 / 239,616 ( 165 % )

    Embedded Multiplier 9-bit elements 4 / 52 ( 8 % )

    PLLs 0 / 4 ( 0 % )

    Global clocks 14 / 16 ( 88 % )

    Maximum fan-out node clk~clkctrl

    Maximum fan-out 2954

    Highest non-global fan-out 695

    Total fan-out 29721

    Average fan-out 3.86

    --- Quote End ---