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Altera_Forum
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17 years ago

Unable to place RAM cells in design

Hi folks, I'm trying to work on an SoPC design. I've used my architecture as an IP and inserted it onto the SoPC having Nios II CPU, jtag-uart, interval timer, on chip memory, and a pio. I'm try...
Altera_Forum's avatar
Altera_Forum
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17 years ago

The design of the architecture is such that I'm using 32 components which in turn instantiates the identical DPRAM cells having 150 bits capacity each read/written 1 bit at a time.

Total memory bits used by the IP is 4800 out of the available 239616 bits.