Unable to place RAM cells in design

This is the summary of my IP's compilation report:

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Total logic elements 1,859 / 18,752 ( 10 % )

-- Combinational with no register 777

-- Register only 224

-- Combinational with a register 858

Logic element usage by number of LUT inputs

-- 4 input functions 492

-- 3 input functions 635

-- <=2 input functions 508

-- Register only 224

Logic elements by mode

-- normal mode 1138

-- arithmetic mode 497

Total registers* 1,082 / 19,649 ( 6 % )

-- Dedicated logic registers 1,082 / 18,752 ( 6 % )

-- I/O registers 0 / 897 ( 0 % )

Total LABs: partially or completely used 133 / 1,172 ( 11 % )

User inserted logic elements 0

Virtual pins 0

I/O pins 45 / 315 ( 14 % )

-- Clock pins 1 / 8 ( 13 % )

Global signals 2

M4Ks 2 / 52 ( 4 % )

Total memory bits 4,800 / 239,616 ( 2 % )

Total RAM block bits 9,216 / 239,616 ( 4 % )

Embedded Multiplier 9-bit elements 0 / 52 ( 0 % )

PLLs 0 / 4 ( 0 % )

Global clocks 2 / 16 ( 13 % )

Average interconnect usage 2%

Peak interconnect usage 4%

Maximum fan-out node clk~clkctrl

Maximum fan-out 1039

Highest non-global fan-out signal quad16:q16|nlfsr10:nlfsr_10|wradd[4]~731

Highest non-global fan-out 520

Total fan-out 8026

Average fan-out 2.72

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