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FPGA_user2's avatar
FPGA_user2
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1 year ago

Unable to get LED blink on the FPGA board Cyclone V 5CGXFC5C6F27C7N

Hello everyone,

I am doing an LED blink program using the FPGA board Cyclone V 5CGXFC5C6F27C7N. I am sharing the Verilog code, .sdc file, and the pin assignment screenshots.
LED Blink codeSDC filePin Planner
The Software version used is Quartus Prime 22.1 Lite Edition; the device is Cyclone V 5CGXFC5C6F27C7N.
The board is customized and does not have an LED on it. So, we connected an LED to an I/O pin named 'light.' The program is run, and when it's programmed on the board, we cannot get the LED to blink.
What could be the reason?
I am new to FPGA.
It would be helpful if anyone could guide me on this.
Thank You.
Hdl

18 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Why does it look like Analysis & Synthesis and the Fitter have not run? Did you fully compile the design? Also note that initial blocks are not synthesizable so you should probably initialize via reset control in the always process block. Any warnings or errors in compilation? What is your indication that the device was successfully programmed? Did the Programmer indicate this (assuming you used a .sof file over a download cable like the USB Blaster)?

    Are you bringing in a 50 MHz clock or 100 MHz? Your .sdc and comment in your code say two different things. The LED could be cycling too quickly for you to see. It would probably be better to put an oscilloscope on the output to see if the signal keeps inverting.

    Way more details needed here about your setup and what you've tried as far as debugging is concerned.

    • FPGA_user2's avatar
      FPGA_user2
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hello sstrell,

      Thank You for the response.

      We have run the Analysis & Synthesis and the Fitter. And the design is fully compiled. The screenshot of the same is attached herewith.

      I have tried to initialize it in the main module itself.

      FPGA code

      I have attached the warnings; there were no errors.

      Warnings


      The programmer indicated 100% success. Screenshot attached.

      Programmer indication

      .sdc format

      Is the .sdc format correct? Are there any other lines to be included?

      The clock we are trying to bring in is 50MHz.

      Once the code was programmed, we got 2.3V on the multimeter for all the output JTAG pins. We don't understand the reason for this. And there is no waveform seen on the oscilloscope. The LED was connected at this PIN_D26 with respect to the ground.

      Please help us regarding this issue.

      Thank You

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    Are you using an Altera board or your custom board?


    For the statement: Once the code was programmed, they got 2.3V on the multimeter for all the output JTAG pins.


    May I know what you meant by this? There is only one JTAG output pin which is - TDO. Do you power the pin with a 2.5V?


    Can you help to measure the clock with the oscilloscope and verify if it is toggling?


    As a sanity check, it is recommended for you to run RTL simulation first.


    Regards,

    Aqid


    • FPGA_user2's avatar
      FPGA_user2
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hello AqidAyman_Intel,

      Sir, I am using a custom board.

      For the statement: Can you help to measure the clock with the oscilloscope and verify if it is toggling?

      Yes, I have checked the clock output in the oscilloscope; it's sinusoidal with a 50 MHz frequency. The IC number is U7. The oscilloscope used was 100MHz, 2GSa/s.

      The RTL simulation is also run.

      RTL simulation

      Could we have a Teams meeting to discuss further about this issue?

      Thank You

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    May I know do you have any updates on this issue?

    Do you need more help?


    Regards,

    Aqid


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    May I know your suggested time and date to have a call meeting for this issue?


    Regadrs,

    Aqid


    • FPGA_user2's avatar
      FPGA_user2
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hello sir,

      Thank You for your reply. We may have the meeting on May 25th, 2024, at 7 AM (PST) if it's ok with you to discuss the issue.

      Thank You

    • FPGA_user2's avatar
      FPGA_user2
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hello Aqid sir,

      Thank You for the reply. I will execute the steps in the design example.

      Regards

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    Okay noted. You can update back to me the results if you want.

    Let me know if you need more support.


    Regards,

    Aqid


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    Is there any update from your side on this? Do you need more support on this or can we close this thread?


    please let me know if you need more help as I am happy to support more.


    Regards,

    Aqid


    • FPGA_user2's avatar
      FPGA_user2
      Icon for New Contributor rankNew Contributor
      1 year ago

      Respected Aqid sir,

      I am sorry for the delayed response.

      The current update is that we couldn't troubleshoot with the help video suggested.

      We are using a custom board, Cyclone V development board Version 2. The Quartus Prime version we are using is Quartus Prime Lite Edition 22.1.

      Query I:

      We have followed these steps to create a New project wizard. Kindly let me know if this is correct.

      1.

      2. Ours is a custom board. Which is the board option we should choose in this? Or is there a way to add the board version at this stage?

      Query II:

      These are the programming steps followed:

      1. USB Blaster cable is detected

      2. When auto-detect is pressed, the device is selected

      3. This error appears after the program is tried to be dumped.

      Are the steps of programming correct? Am I missing out on anything?

      As mentioned, no LEDs or push switches are on the custom board. One GPIO pin was set as the output pin, and an LED was connected. The pin is given an I/O standard of 3.3V - LVTTL, with a current strength of 16mA. As I understand, LED requires a 20mA drive current. Is this probably the issue of why the LEDs aren't turning on?

      Is there a solution for this?

      Your support would be precious.

      Thank You.

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    My suggestion is to copy the Verilog code only into your top file of your design. Other than that, you need to ensure it is suits with the device configuration as you are using a custom board.


    • FPGA_user2's avatar
      FPGA_user2
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hello,

      Thank You for the reply. How do we check if it suits the device configuration? This is where we are stuck.

      Can the custom board details be added to the Quartus Prime software?

      Thank You.

      Regards

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Based on your last question on the steps you followed, in the first step, you no need to choose the board since you are using custom board. You just choose the FPGA device OPN that the board is using.


    Then, can you tried to reprogram the device using the programmer?


    • FPGA_user2's avatar
      FPGA_user2
      Icon for New Contributor rankNew Contributor
      1 year ago

      Sir,

      Thank you for your reply.

      I have selected only the FPGA device OPN that the board uses in the first step. I tried to reprogram, but there was no result.

      Regards

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    As we do not receive any response from you on the previous reply have been provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you by replying to this thread.