Forum Discussion
Why does it look like Analysis & Synthesis and the Fitter have not run? Did you fully compile the design? Also note that initial blocks are not synthesizable so you should probably initialize via reset control in the always process block. Any warnings or errors in compilation? What is your indication that the device was successfully programmed? Did the Programmer indicate this (assuming you used a .sof file over a download cable like the USB Blaster)?
Are you bringing in a 50 MHz clock or 100 MHz? Your .sdc and comment in your code say two different things. The LED could be cycling too quickly for you to see. It would probably be better to put an oscilloscope on the output to see if the signal keeps inverting.
Way more details needed here about your setup and what you've tried as far as debugging is concerned.
- FPGA_user21 year ago
New Contributor
Hello sstrell,
Thank You for the response.
We have run the Analysis & Synthesis and the Fitter. And the design is fully compiled. The screenshot of the same is attached herewith.
I have tried to initialize it in the main module itself.
FPGA code
I have attached the warnings; there were no errors.
Warnings
The programmer indicated 100% success. Screenshot attached.Programmer indication
.sdc format
Is the .sdc format correct? Are there any other lines to be included?
The clock we are trying to bring in is 50MHz.
Once the code was programmed, we got 2.3V on the multimeter for all the output JTAG pins. We don't understand the reason for this. And there is no waveform seen on the oscilloscope. The LED was connected at this PIN_D26 with respect to the ground.
Please help us regarding this issue.
Thank You