Transceiver Toolkit Pattern Generator/Checker Memory Map

Look at the source code of Pattern Generator, and Pattern Checker IP cores. The files are generated by Qsys.

That's what I was doing in my designs.

Thanks,

Evgeni

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My question is whether anyone knows the Memory Map locations for this?

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Yes, its in an older version of the Embedded Peripherals IP Guide ... I would upload the whole PDF but the forum has a file size limit ... here's the Chapter you need.

Yes, it is totally lame that Altera has deleted this chapter and not included in the handbook (which it has done with some of the other chapters it deleted from this doc).

Cheers,

Dave

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Yes, its in an older version of the Embedded Peripherals IP Guide ... I would upload the whole PDF but the forum has a file size limit ... here's the Chapter you need.

Yes, it is totally lame that Altera has deleted this chapter and not included in the handbook (which it has done with some of the other chapters it deleted from this doc).

Cheers,

Dave

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Hi Dave,

Thanks for sharing this doc. I have been looking for it for some time also.

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Hi all,

I have modified and instantiated a 10G Transceiver example into a Stratix V FPGA. I have also incorporated the JTAG Master, Pattern Generator, and Pattern Checker. The design works well and I want to access the test functions via the main Avalon master and not the JTAG master. Here is the problem, I have not found the memory map for either the Generator or Checker. I do find some docs for streaming versions, but this is not the same one used by the TTK. The TTK shows options of PRBS7, PRBS15, PRBS23, PRBS31, Low Frequency, High Frequency, and BYPASS, plus the Start, Stop, and Reset buttons. Also, the error counters. I have used Signal Tap to get these values, but that is prone to mistakes.

My question is whether anyone knows the Memory Map locations for this?

BTW, the 10G design has been around a while and Altera may changed the design/docs. In my design, I used the QSYS duplicate function.

Thanks in advance.

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By the way, probably you could try to start by customizing the toolkit design example. You can leverage the existing pattern generator/checker and use it with TTK.

Thx Dave,

That is what I was looking for. BTW, Altera seems to have hidden the field for "BYPASS". It is bit 8 of offset 1 for both the generator and checker. The memory map simply says "Reserved". You can see the BYPASS function in the TTK.

--- Quote Start ---

Yes, its in an older version of the Embedded Peripherals IP Guide ... I would upload the whole PDF but the forum has a file size limit ... here's the Chapter you need.

Yes, it is totally lame that Altera has deleted this chapter and not included in the handbook (which it has done with some of the other chapters it deleted from this doc).

Cheers,

Dave

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Hi Dave,

Thanks for sharing this useful info.