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Hi all,
I have modified and instantiated a 10G Transceiver example into a Stratix V FPGA. I have also incorporated the JTAG Master, Pattern Generator, and Pattern Checker. The design works well and I want to access the test functions via the main Avalon master and not the JTAG master. Here is the problem, I have not found the memory map for either the Generator or Checker. I do find some docs for streaming versions, but this is not the same one used by the TTK. The TTK shows options of PRBS7, PRBS15, PRBS23, PRBS31, Low Frequency, High Frequency, and BYPASS, plus the Start, Stop, and Reset buttons. Also, the error counters. I have used Signal Tap to get these values, but that is prone to mistakes.
My question is whether anyone knows the Memory Map locations for this?
BTW, the 10G design has been around a while and Altera may changed the design/docs. In my design, I used the QSYS duplicate function.
Thanks in advance.
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By the way, probably you could try to start by customizing the toolkit design example. You can leverage the existing pattern generator/checker and use it with TTK.
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