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Altera_Forum
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11 years ago

Transceiver Toolkit Pattern Generator/Checker Memory Map

Hi all, I have modified and instantiated a 10G Transceiver example into a Stratix V FPGA. I have also incorporated the JTAG Master, Pattern Generator, and Pattern Checker. The design works well ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Look at the source code of Pattern Generator, and Pattern Checker IP cores. The files are generated by Qsys.

That's what I was doing in my designs.

Thanks,

Evgeni