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Altera_Forum
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10 years ago

Transceiver Toolkit Pattern Generator/Checker Memory Map

Hi all, I have modified and instantiated a 10G Transceiver example into a Stratix V FPGA. I have also incorporated the JTAG Master, Pattern Generator, and Pattern Checker. The design works well ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

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My question is whether anyone knows the Memory Map locations for this?

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Yes, its in an older version of the Embedded Peripherals IP Guide ... I would upload the whole PDF but the forum has a file size limit ... here's the Chapter you need.

Yes, it is totally lame that Altera has deleted this chapter and not included in the handbook (which it has done with some of the other chapters it deleted from this doc).

Cheers,

Dave