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Altera_Forum
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11 years ago

Transceiver Toolkit Pattern Generator/Checker Memory Map

Hi all, I have modified and instantiated a 10G Transceiver example into a Stratix V FPGA. I have also incorporated the JTAG Master, Pattern Generator, and Pattern Checker. The design works well ...
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Altera_Forum
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11 years ago

Thx Dave,

That is what I was looking for. BTW, Altera seems to have hidden the field for "BYPASS". It is bit 8 of offset 1 for both the generator and checker. The memory map simply says "Reserved". You can see the BYPASS function in the TTK.