Altera_ForumHonored Contributor10 years agoTransceiver Toolkit Pattern Generator/Checker Memory Map Hi all, I have modified and instantiated a 10G Transceiver example into a Stratix V FPGA. I have also incorporated the JTAG Master, Pattern Generator, and Pattern Checker. The design works well ...Show More
Recent DiscussionsHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorConnection bit order between hierarchyCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: