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Altera_Forum's avatar
Altera_Forum
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10 years ago

Timings - am I overthinking this?

I'm just learning VHDL & FPGAs (as a hobby). I studied electronic engineering at degree level over 20 years ago, but we didn't do anything with FPGAs then (they were still a bit 'leading edge'). Back then electronics were slower, and we worked with discrete logic (74LS) a lot. Timing was important (things like RAM had multi-ns setup/hold times and hundreds of ns access time)

I'm using a Cyclone II (DE1 board) and I want to have some internal memory. I can create the internal memory fine.

Looking at examples, I can use a process and do something like:

process(clk)

begin

if (rising_edge(clk)) then

RAM_Addr <= myaddr;

RAM_Clk <= '1';

end if;

end process;

And that will work (for setting the read address - obviously I need to do more to get the data out).

So, I have a 2 clock cycle (1) set address, clock high, (2) read data, clock low, (1) set address, etc

But, if I look at the datasheet for the Cyclone II, on page 5-17, it says that I need 35ps setup time for the address before the clock. From my understanding of VHDL, that's not what I've designed - I've designed that the address & clock change simultaneously. I know 35ps is not a lot of time, but it's not 0ps.

Now, it seems to work OK - but is that (a) because the synthesis tools know about the timing requirements and sort it out, (b) I'm lucky, (c) something else?

I could add an extra clock cycle into the reading algorithm, so it does (1) set address, (2) set clock high, (3) read data, clock low, (1) set address etc, but that'll complicate things and slow it down unnecessarily if it's not needed.

(In the 'old' days, I may have added an otherwise-unneeded buffer or gate to delay the clock by 7ns or so without having to add extra states).

Am I overthinking (and overcomplicating) it? Or should I be adding the extra steps in to be safe?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    It is not over thinking but you are mixing up between clock cycles and register timing requirements.

    For things like setup/hold it is related to register timing requirement at each clock edge. This is an matter left to the tool to tell you pass/fail, though eventually you need to improve on it if fail.

    clock cycle requirement issues (clock latency or call it sample latency/availability etc) is totally different issue. It is related to functionality you want for example you wrote to ram data at same clock cycle as address but read out one or so clock later relative to address.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    So, that means that reading using "(1) set address, clock high, (2) read data, clock low, (1) set address, etc" is OK? (unless I get told otherwise)

    (It's only a 50MHz clock running this cycle so well within the internal RAM's capability)

    I was hoping that was the case, and it certainly makes things a lot simpler :-)

    (For writing to the memory, I tend to do (1)set address/data, clock low, (2) clock high, (1) set address/data, clock low, so setup/hold weren't worrying me there)
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    In FPGAs we do not do things when clock is low or high but rather do sampling on clock edge (usually rising edge). This the fundamental point and a vhdl process is used to infer that though some beginners use instants of clocked registers.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yeah, I get that processes are done on clock edges,

    So, when my 50MHz clock has its first rising edge, I am setting the address onto the memory address inputs, and taking the memory clock high (causing a rising edge there). Then, when the 50MHz clock has its second rising edge, I am reading the data from the memory data outputs, and taking the memory clock low (causing a falling edge, which does nothing, except make it ready for the next rising edge).

    That's what I meant - sorry it wasn't clear :-)
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If you are using an internal memory block (and even an external RAM with a synchronous interface) then you are better off using the same clock signal in your logic and the memory module. Generating clock signals from FPGA logic can lead to a whole bunch of problems.

    The major difference between "old school designs" with 74LS ttl chips and the more "modern" FPGAs is that the FPGA is meant to be used in synchronous designs. Just connect both your logic and the RAM block to the same 50MHz clock. On the first rising edge you set the address, the memory block registers it on the second rising edge, and you can read the data back on the third rising edge (that is supposing you configure the memory block with a one-cycle latency). AFAIK the memory blocks in the Cyclone II do not support asynchronous mode and there is at least one latency cycle.

    If you look at the datasheet on page 8-10 you'll see a timing diagram.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks for that - that makes sense.

    Annoyingly, what I've got works - almost. I think some of the problem is crossing clock domains (which I'm going to start another question on) but some of it may be this as well. I think I'm going to have to throw away a lot of what I've done, and start again with a whole different way of thinking... Not too much of a problem because I am learning by my mistakes ;-)