Timings - am I overthinking this?

If you are using an internal memory block (and even an external RAM with a synchronous interface) then you are better off using the same clock signal in your logic and the memory module. Generating clock signals from FPGA logic can lead to a whole bunch of problems.

The major difference between "old school designs" with 74LS ttl chips and the more "modern" FPGAs is that the FPGA is meant to be used in synchronous designs. Just connect both your logic and the RAM block to the same 50MHz clock. On the first rising edge you set the address, the memory block registers it on the second rising edge, and you can read the data back on the third rising edge (that is supposing you configure the memory block with a one-cycle latency). AFAIK the memory blocks in the Cyclone II do not support asynchronous mode and there is at least one latency cycle.

If you look at the datasheet on page 8-10 you'll see a timing diagram.