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Honored Contributor
Honored ContributorTimings - am I overthinking this?
I'm just learning VHDL & FPGAs (as a hobby). I studied electronic engineering at degree level over 20 years ago, but we didn't do anything with FPGAs then (they were still a bit 'leading edge'). Back...
Altera_ForumHonored Contributor
Honored ContributorSo, that means that reading using "(1) set address, clock high, (2) read data, clock low, (1) set address, etc" is OK? (unless I get told otherwise)
(It's only a 50MHz clock running this cycle so well within the internal RAM's capability) I was hoping that was the case, and it certainly makes things a lot simpler :-) (For writing to the memory, I tend to do (1)set address/data, clock low, (2) clock high, (1) set address/data, clock low, so setup/hold weren't worrying me there)
