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Altera_Forum
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10 years ago

Timings - am I overthinking this?

I'm just learning VHDL & FPGAs (as a hobby). I studied electronic engineering at degree level over 20 years ago, but we didn't do anything with FPGAs then (they were still a bit 'leading edge'). Back...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

In FPGAs we do not do things when clock is low or high but rather do sampling on clock edge (usually rising edge). This the fundamental point and a vhdl process is used to infer that though some beginners use instants of clocked registers.