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Altera_Forum's avatar
Altera_Forum
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11 years ago

Timings - am I overthinking this?

I'm just learning VHDL & FPGAs (as a hobby). I studied electronic engineering at degree level over 20 years ago, but we didn't do anything with FPGAs then (they were still a bit 'leading edge'). Back...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks for that - that makes sense.

Annoyingly, what I've got works - almost. I think some of the problem is crossing clock domains (which I'm going to start another question on) but some of it may be this as well. I think I'm going to have to throw away a lot of what I've done, and start again with a whole different way of thinking... Not too much of a problem because I am learning by my mistakes ;-)