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Honored Contributor
Honored ContributorTimings - am I overthinking this?
I'm just learning VHDL & FPGAs (as a hobby). I studied electronic engineering at degree level over 20 years ago, but we didn't do anything with FPGAs then (they were still a bit 'leading edge'). Back...
Altera_ForumHonored Contributor
Honored ContributorYeah, I get that processes are done on clock edges,
So, when my 50MHz clock has its first rising edge, I am setting the address onto the memory address inputs, and taking the memory clock high (causing a rising edge there). Then, when the 50MHz clock has its second rising edge, I am reading the data from the memory data outputs, and taking the memory clock low (causing a falling edge, which does nothing, except make it ready for the next rising edge). That's what I meant - sorry it wasn't clear :-)
