Timings - am I overthinking this?

It is not over thinking but you are mixing up between clock cycles and register timing requirements.

For things like setup/hold it is related to register timing requirement at each clock edge. This is an matter left to the tool to tell you pass/fail, though eventually you need to improve on it if fail.

clock cycle requirement issues (clock latency or call it sample latency/availability etc) is totally different issue. It is related to functionality you want for example you wrote to ram data at same clock cycle as address but read out one or so clock later relative to address.