Timing driven synthesis option is not found in Quartus 19.4 when Agilex device is selected

If you refer to https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_synth_timing_driven_synthesis.htm

This options does not support agilex device.

Unlike standard edition, you will have to use SDC files on the fitter plan stage itself.

Timing driven synthesis was enable by default in Pro. You do not need to do any thing unless you want to disable it.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-compiler-18-1.pdf

page 11

As long as you put your constrain sdc files in assignemtn -> setting -> timing analyzer. it should be sufficient to let Quartus know that you had use your timing constrain.

Do you have a simple design example for Pro and Std? I will make a comparison here and get back to you.

Basically, I do think that synthesis steps should throw syntax error from the SDC since sdc is being taking care of in synthesis when using timing driven synthesis.

base on your design. I move it to standard of Quartus. And purposely set the incorrect port to your sdc.

create_clock -name clk -period 10 [get_ports clockABC]

When I run the synthesis on both pro and std. I don't see any sdc error or warning. this is for apple to apple comparison.

Internally, it should. However, they don't check on sdc error. Which means, it will take the sdc that is written incorrectly, either ignore it and implement wrongly on it. Thus, when your synthesis, you might not get accurate timing synthesis.

However, in fitter stage, those sdc written will still be catch and user had to modify it there.

you can still check in compilation report -> synthesis -> settings -> settings

Over there, you should see this option was on.

Let me check with developer, Agilex are new device.