Timing driven synthesis option is not found in Quartus 19.4 when Agilex device is selected

Internally, it should. However, they don't check on sdc error. Which means, it will take the sdc that is written incorrectly, either ignore it and implement wrongly on it. Thus, when your synthesis, you might not get accurate timing synthesis.

However, in fitter stage, those sdc written will still be catch and user had to modify it there.