Solved
Forum Discussion
KennyT_altera
Super Contributor
6 years agoDo you have a simple design example for Pro and Std? I will make a comparison here and get back to you.
Basically, I do think that synthesis steps should throw syntax error from the SDC since sdc is being taking care of in synthesis when using timing driven synthesis.
- Sajith_K_Intel6 years ago
New Contributor
I can provide a sample design of Pro, not Standard as i do not have it.
As you said, timing driven synthesis is by default ON. then why do yo think synthesis will not consider sdc errors?
In the attached example, i do not see any info messages about sdc during synthesis.