Forum Discussion
Sajith_K_Intel
New Contributor
New ContributorTiming driven synthesis option is not found in Quartus 19.4 when Agilex device is selected
When using Agilex device in Quartus 19.4, There is no option to set Timing driven synthesis (in advanced synthesis settings). Hence I am not sure if SDC file will be considered during synthesis. Fro...
For Agilex, this feature had been drop
KennyT_altera
Super Contributor
Super Contributorbase on your design. I move it to standard of Quartus. And purposely set the incorrect port to your sdc.
create_clock -name clk -period 10 [get_ports clockABC]
When I run the synthesis on both pro and std. I don't see any sdc error or warning. this is for apple to apple comparison.
Sajith_K_IntelNew Contributor
New ContributorYes you are right.
This is why I doubt if Timing information is considered or not during synthesis
