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Sajith_K_Intel's avatar
Sajith_K_Intel
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Timing driven synthesis option is not found in Quartus 19.4 when Agilex device is selected

When using Agilex device in Quartus 19.4, There is no option to set Timing driven synthesis (in advanced synthesis settings). Hence I am not sure if SDC file will be considered during synthesis. Fro...
  • KennyT_altera's avatar
    KennyT_altera
    6 years ago

    For Agilex, this feature had been drop

KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

base on your design. I move it to standard of Quartus. And purposely set the incorrect port to your sdc.

create_clock -name clk -period 10 [get_ports clockABC]

When I run the synthesis on both pro and std. I don't see any sdc error or warning. this is for apple to apple comparison.

Sajith_K_Intel's avatar
Sajith_K_Intel
Icon for New Contributor rankNew Contributor
6 years ago

Yes you are right.

This is why I doubt if Timing information is considered or not during synthesis