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KennyT_altera
Super Contributor
6 years agoIf you refer to https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_synth_timing_driven_synthesis.htm
This options does not support agilex device.
Unlike standard edition, you will have to use SDC files on the fitter plan stage itself.
- Sajith_K_Intel6 years ago
New Contributor
Do you know why it is not there for Agilex? or do we have an alternate option wgen using Agilex?
In such a case, how do we make sure synthesis is aware of my timing constraints to optimize the design?