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KennyT_altera
Super Contributor
6 years agoTiming driven synthesis was enable by default in Pro. You do not need to do any thing unless you want to disable it.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-compiler-18-1.pdf
page 11
As long as you put your constrain sdc files in assignemtn -> setting -> timing analyzer. it should be sufficient to let Quartus know that you had use your timing constrain.
- Sajith_K_Intel6 years ago
New Contributor
If so, shouldnt there be a mention about SDC in synthesis log? Bit it is not doing.
I think synthesis step then should throw syntax errors from SDC file. Somehow this is not happening.