Timing Analyzer: Failing Paths - Arria10

Hello,

I am currently working on a video switcher that consists of four video mixers within it, using a Arria10. The board has 12x12 inputs/outputs. My FPGA revision compiles without any issues and seems to be performing correctly, except there is some inconsistent behavior that I believe is caused by these failed timing paths. I have tried multiple different optimizations settings and synthesis/fitter settings, but have not had any luck fixing the issue. Each time I compile, a random input will go out within a mixer. I will provide pictures and as much information as I can. For example, input 2 will be displayed and working for mixers 1,2, and 4, but will randomly be out within mixer 3. The next compile with no changes could cause input 2 to come back within mixer 3, but will be out within mixer 2. This behavior is inconsistent and does not make much sense to me.

The failed timing paths correlate with the arria10_hps_0 and the ddr4_fpga components. I will provide screenshots below of everything I have mentioned as well as my timing analyzer report.

arria10_hps timing reportddr4_fpga timing reportFull timing summary

The missing_input_example.jpg provided shows how mixers 1,2, and 4 have all the inputs, but for some reason the second input on mixer 3 is out. Do not worry about duplicate inputs or the blue screen inputs, I am just doing that for testing.

missing input example

I am really just trying to understand what is causing this behavior. If someone could lead me in the right direction that would be great. If you have any questions or need me to provide more information, feel free to ask!

Thank you,

Evan

evanh@javs.com