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EvanHamiltonJAVS
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1 year ago

Timing Analyzer: Failing Paths - Arria10

Hello, I am currently working on a video switcher that consists of four video mixers within it, using a Arria10. The board has 12x12 inputs/outputs. My FPGA revision compiles without any issues and ...
Compilation
Hdl
Platform
Timing
EvanHamiltonJAVS's avatar
EvanHamiltonJAVS
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1 year ago

Hi Sheng,

Yes I am using maximum performance compiler settings. Also, I already have memory mapped interconnect pipelines. If you need more information, just let me know!

Thanks,

Evan

evanh@javs.com