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EvanHamiltonJAVS's avatar
EvanHamiltonJAVS
Icon for New Contributor rankNew Contributor
1 year ago

Timing Analyzer: Failing Paths - Arria10

Hello, I am currently working on a video switcher that consists of four video mixers within it, using a Arria10. The board has 12x12 inputs/outputs. My FPGA revision compiles without any issues and ...
Compilation
Hdl
Platform
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Since you're already using Maximum Performance settings and full interconnect pipelines.

Could you try to add pipeline register in between those failing nodes?

Also try to run seed sweep to see any improvements?


Thanks,

Regards,

Sheng