Timing analysis on EMIF block

Hi,

Do you made some modification to the IP?

I created a design and used the emif user clock.

I can see the *core_usr_clk is recognize by default.

hi,

I did not make any change to the IP. I just regenerate it and use it in the project. I am using Quartus 18.1. You can see that there is no user clock in the list of clock for the get_clocks command. I name it emif_usr_clk and it is not in the list.

Have you connected this clock up to your user logic yet? Not sure if you're using Platform Designer or not, but in the Block Symbol diagram or the instantiation template for the IP, do you see the clock output enabled?

sstrell,

I check out the IP, initiate it, regenerate the IP (during the first compilation) and use it from there. The design is actually working in hardware (on Intel development board). I just want to do timing analysis to make sure that timing is o.k. and i discover this issue.

I asked because if it was not connected, it would not show up as a clock in the Name Finder, like you show in your screenshot. The signal has to drive a clock input to be recognized as a clock domain. Try using the get_pins filter just to make sure it's not connected incorrectly.

Can you run Report Clocks in the timing analyzer and see this clock there?

Thanks sstrell.

To run report clock.

Goto 'reports' tab, point to 'diagnostic' and click 'report clocks'.

the attached screen shows that the emif user clock is not in the clock report. I also attache the RTL screen shot showing that user clock is connected to other device (see the red highlighted net). This case is very strange.

I can send you the design if you want.

(it looks like i can only attach one file at a time, so check the next two posts for other files)

RTL showing user clock is connected to other logic.

RTL showing user clock is connected to other logic.

I will suggest you generate the example design and see if the example design have the same problem. If example design usr clk is being detected, then make comparison between your design with example design.