Thanks Rysc. I appreciate your advice.
I did the report and found 6 setup paths. They are from bus_tri_d to my generated virtual clock.
slack from node to node launch clock latch clock relat. clock_skew data_delay
-20.747 fmrc_i|bus_tri_d|q flash_ce_n not_a_clock Nand_flash_wr_strobe 5.000 0.000 5.597
I noticed when I was writing my SDC constraints for this interface that Timequest was complaining that I had not constrained
the bus_tri_d node. For a tristate signal I did not believe this was necessary. Here are my sdc write memory constraints. Is there some
not quite right in here that is making Timequest get a bit upset
# Read memory access time
set tREH_min 10
# Read memory hold time
set tREA_max 20
# Create write strobe signal maximum 25MHz but use 50MHz just incase. This is the virtual clock
create_generated_clock -name Nand_flash_wr_strobe -source [get_nets {dctu_i|a_uniphy_i|a_uniphy_inst|pll0|afi_phy_clk}] -divide_by 3 [get_ports {flash_we_n}]
# Constrain command latch cycle
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -min -5.00 [get_ports {flash_cle}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -max 10.00 [get_ports {flash_cle}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -min -5.00 [get_ports {flash_ce_n}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -max 20.00 [get_ports {flash_ce_n}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -min -5.00 [get_ports {flash_ale}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -max 10.00 [get_ports {flash_ale}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -min -5.00 [get_ports {flash_wp_n}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -max 10.00 [get_ports {flash_wp_n}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -min -5.00 [get_ports {flash_data[*]}]
set_output_delay -add_delay -clock { Nand_flash_wr_strobe} -max 10.00 [get_ports {flash_data[*]}]
set_multicycle_path -from [get_clocks {dctu_i|a_uniphy_i|a_uniphy_inst|pll0|pll_afi_clk}] -to [get_clocks {Nand_flash_wr_strobe}] -setup -end 6
set_multicycle_path -from [get_clocks {dctu_i|a_uniphy_i|a_uniphy_inst|pll0|pll_afi_clk}] -to [get_clocks {Nand_flash_wr_strobe}] -hold -end 5
# set false path on tri-state enable and cut timing paths between bi-dir pads that don't require timing now
set_false_path -from {fmrc:fmrc_i|bus_tri_d*} -to {flash_*}
set_false_path -from [get_clocks {Nand_flash_wr_strobe}] -to [get_clocks {dctu_i|a_uniphy_i|a_uniphy_inst|pll0|pll_afi_clk}]
Essentially what I am doing here is creating a virtual clock that represents the write strobe signal that clocks in the data to the NAND flash
device. I then create setup and hold constraints for the signals that are sampled by the write strobe line. I also add a multicycle constraint to
open up the size of the timing window. I finally do some cutting on some paths. You can see I have cut the path between bus_tri_d and all flash
signals. Below is what my verilog looks like
//tristate flash bus signals when not in use
assign flash_cle = (bus_tri_d) ? 1'bz : cle_d;
assign flash_ale = (bus_tri_d) ? 1'bz : ale_d;
assign flash_ce_n = (bus_tri_d) ? 1'bz : ce_n_d;
assign flash_we_n = (bus_tri_d) ? 1'bz : we_n_d;
assign flash_re_n = (bus_tri_d) ? 1'bz : re_n_d;
Any guidance you can provide would be most appreciated
C
Honored Contributor
