Timequest: Tri-state node assumed to be a clock

According to your diagram clearly the bus_tri_d is not clock in the usual sense, neither is there any other register after it.

so either timequest is going wrong or is misled or may be it has different rules for tristate buffer- just a guess.

I can imagine that a tristate buffer OE will trigger the buffer output (as if like a clock on a register). This is a point of transition that you may need to control its timing. As you have no registers in the flash but constraints required for the flash signals then you might be helped to control the buffer output transition by surrendering to timequest rules and declaring bus_tri_d as clock.