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Altera_Forum
Honored Contributor
11 years agoIt looks like you have badly confused timequest and beaten it.
Moreover your new multicycle does not look right. What you need is simpler. the flash needs certain timing requirements (this has nothing to do with latching clock as it is asynchronous). All you need a constraint to keep io delays under control and you have plenty of margin I assume. I suggest you use system clock as your reference and apply set_output_delay relative to it to all your signals.