Timequest: Tri-state node assumed to be a clock

So the analysis you're seeing is "clock as data", whereby something constrained as a clock is then analyzed as data into another domain. An example of this might be a clock you generate with a divide by two register, and then sample it in the higher speed domain so you know edge it's on. It's still not showing you any paths where the tri-state is being used as an actual clock. I don't think you want the analysis it's doing and should get rid of it. I'm not sure why you're getting that original warning and can't tell from the info provided. You may want to file an SR or ignore it, if you know you're analyzing the interface correctly.

(My other thought is that you have a signal coming into the FPGA from one of those flash pins that's used as a clock. In that case, it may be looking at the tri-state register wrapping around into that port too. I would have expected it to show up in your report_timing though. Regardless, you don't want to analyze that path as a clock if that's what is going on.)