Timequest: Tri-state node assumed to be a clock

Kaz,

Thanks for your reply. I have attached a picture showing some extra levels of flash_re_n.

The flash chip is asynchronous relying on data being sampled using a write or read strobe signal.

The setup is that an external microcontroller can read or write to the NAND flash chip. The FPGA

can read or write to the NAND Flash chip as well. This is why I have to use a tri-state so the

lines are freed up during the micro to NAND flash chip communication. The micro can also

read and write to the FPGA but that's a different story.

C