Forum Discussion
New ContributorSynthesis Hung for Large Designs
I am trying to synthesize a design that includes:
- 64x64x64x128 Single-Port RAM
- 64x64x64x32 Single-Port ROM
- 64x64x64x64 Two-Port RAM
on a 1SG280LN2F43E1VG device with Quartus 20.3 and I have found that the tool is stuck at 33% of the Analysis & Synthesis phase for 3 days. There are no meaningful warnings about the RTL design and I believe I have enough resources on the device for this design.
For what it's worth, I was able to implement both a design that includes:
- 16x16x16x128 Single-Port RAM
- 16x16x16x32 Single-Port ROM
- 16x16x16x64 Two-Port RAM
and a design that includes:
- 32x32x32x128 Single-Port RAM
- 32x32x32x32 Single-Port ROM
- 32x32x32x64 Two-Port RAM
See attached PNG, it summarizes some of the results for both the successfully implemented designs.
I was running into a similar issue before, but the tool ended up synthesizing the design (albeit a slightly different one) in 30 hours, it then took 4 hours to get through Timing Analysis. Unfortunately, I no longer have information from that run.
23 Replies
- RichardT_altera
Super Contributor
Sorry for idling for some time. Do you able to solve the issue?
Have you try to the design with another computer?
Try and reinstall the latest Quartus Pro 20.4 to see if the issue persists.
apducimoYes I have tried on multiple machines each with their own installation of Quartus Pro 20.4. I even tried earlier version of Quartus Pro and git the same issue. I only update to Quartus Pro 20.4 to prevent the request to run with the latest version of the tool
- RichardT_altera
Could you help to share your design so I could test it from my side?
- RichardT_altera
I encounter below error, do you have this error before?
Error(13305): Verilog HDL error at md_lr_top_64x64x64.sv(254): can't find port "user_reset"
- apducimo
No. I was not seeing this error. From the sounds of it, you are not using the IP as I delivered it. Perhaps you have upgraded it to the point where the IP no longer has the pins that it once had.
- RichardT_altera
I have ask the engineering to check on this abnormal behavior. Will let you know once there is update.
- apducimo
So you were able to recreate the issue, correct?
- RichardT_altera
Yes, I am able to duplicate the issue with Quartus stuck at 33% Analysis & Synthesis stage.
