Forum Discussion
RichardT_altera
Super Contributor
5 years agoI have ask the engineering to check on this abnormal behavior. Will let you know once there is update.
- apducimo5 years ago
New Contributor
So you were able to recreate the issue, correct?
- RichardT_altera5 years ago
Super Contributor
Yes, I am able to duplicate the issue with Quartus stuck at 33% Analysis & Synthesis stage.
- RichardT_altera5 years ago
Super Contributor
You mentioned previously that you are able to implement design with
16x16x16x128 Single-Port RAM
16x16x16x32 Single-Port ROM
16x16x16x64 Two-Port RAM
and32x32x32x128 Single-Port RAM
32x32x32x32 Single-Port ROM
32x32x32x64 Two-Port RAMCould you help to share the .qar design files that is able to pass the Analysis and Synthesis? Either 32 or 16 will do.