apducimoNew Contributor5 years agoSynthesis Hung for Large Designs I am trying to synthesize a design that includes: 64x64x64x128 Single-Port RAM 64x64x64x32 Single-Port ROM 64x64x64x64 Two-Port RAM on a 1SG280LN2F43E1VG device with Quartus 20.3 and I have fou...Show MoreCapture.PNG105 KB
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: