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apducimo's avatar
apducimo
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5 years ago

Synthesis Hung for Large Designs

I am trying to synthesize a design that includes: 64x64x64x128 Single-Port RAM 64x64x64x32 Single-Port ROM 64x64x64x64 Two-Port RAM on a 1SG280LN2F43E1VG device with Quartus 20.3 and I have fou...
RichardT_altera's avatar
RichardT_altera
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5 years ago

I encounter below error, do you have this error before?

Error(13305): Verilog HDL error at md_lr_top_64x64x64.sv(254): can't find port "user_reset"



apducimo's avatar
apducimo
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5 years ago

No. I was not seeing this error. From the sounds of it, you are not using the IP as I delivered it. Perhaps you have upgraded it to the point where the IP no longer has the pins that it once had.