Synthesis - Incorrect SystemVerilog interface parameter override

I have come across an issue where Quartus Pro (21.x) Synthesis incorrectly resolves an interface parameter to its default value rather than the value with which it should've been overridden by the interface instance. Moreover, it only seems to partially affect usage of that parameter within the interface. For example, I have a use case where an interface is declared as the following:

interface mem_if #( int ADDR_W = 4, int DATA_W = 1 ) ( input clk );

   localparam logic [DATA_W - 1:0] INIT_V [2 ** ADDR_W] = '{default: '1};

   logic [ADDR_W - 1:0] addr;
   logic [DATA_W - 1:0] idat, odat;
   logic                wren;

   modport mem
     (
      input  clk, addr, wren, idat,
      output odat
     );

endinterface : mem_if

This interface is instantiated in a top-level module to connect another module:

module mem_wrapper #( int ADDR_W = 5, int DATA_W = 8 )
...
   mem_if #( ADDR_W, DATA_W ) mem_if ( i_clk_a );
   mem mem ( mem_if );
...
endmodule : mem_wrapper

"mem" internally references its interface's ADDR_W and DATA_W parameters as well as INIT_V. In the "mem" instance shown above, ADDR_W and DATA_W are correctly overridden with the instance values 5 and 8 respectively. However, INIT_V's dimensions remain defined as per the interface's default parameter values, leading to a synthesis error when trying to access its array elements. A few additional comments:

• It doesn't matter that INIT_V is a localparam; having it instead defined as an interface parameter leads to the same problem.
• I've tried different ways of defining INIT_V; for example, having it as a vector (single-dimension) whose length is determined by DATA_W * (2 ** ADDR_W). This problem still happens.

In the end, this seems to be a parameter dependence issue for interface definitions. I have attached the complete source code and Quartus Pro project files of the example above, which reproduces the problem I have described; here's the error returned after synthesis (note how the reported range references the array dimensions based on the default values of ADDR_W and DATA_W):

Error(13224): Verilog HDL or VHDL error at mem.sv(7): index 16 is out of range [0:15] for 'INIT_V' 

It would be great if this could be resolved in the next release of Quartus Pro (or a patch for the current release as well) since this is such a simple use case of parameterized interfaces, which Quartus claims support.