ContributionsMost RecentMost LikesSolutionsRe: Questa license option not listed in the SSLC Yes, I was able to generate it a few weeks after posting this question. I believe that, initially, the problem was due to attempting to follow these steps prior to the expiration date of the current license at the time, as I was able to do so on a later date; however, the license file at first was basically empty (it only had some comments) and it wouldn't work at all. I waited a few more days and after that I was able to generate the license file properly. Questa license option not listed in the SSLC I am trying to generate a license for "Questa* Intel® FPGA Starter Edition" but no option for that is listed under the "Sign up for Evaluation or Free Licenses" menu in the SSLC. I have generated similar licenses last year and the year before with my existing account, so I am not sure why this time I am unable to do it. Re: Unable to get past SSLC Email Verification @AR_A_Intel will you provide an update on the status of my account? Re: Synthesis - Incorrect SystemVerilog interface parameter override That's great, thank you for sharing additional details @ShengN_Intel Re: Unable to get past SSLC Email VerificationI have sent all the details and haven’t received any feedback. I still cannot access the SSLC.Re: Unable to get past SSLC Email VerificationIt has been like this for months. Not knowing how I was supposed to approach this, I tried opening a support ticket and have been asked to post the problem in this forum. Can you fix it?Unable to get past SSLC Email Verification Hi I have been trying to get access to Intel's SSLC but I have never received the verification email as shown in the attached screenshot. It has been like this for quite some time; I have repeatedly checked my email's spam box as well and no such email has been sent to me. SolvedRe: Synthesis - Incorrect SystemVerilog interface parameter override @ShengN_Intel This is issue hasn't been fixed in Quartus Pro 22.3. Re: Synthesis - Incorrect SystemVerilog interface parameter override Thank you, @ShengN_Intel Re: Synthesis - Incorrect SystemVerilog interface parameter override Thank you, @ShengN_Intel . I'd appreciate if you could share their feedback once you hear from them.